dr hab. inż. Wojciech Sułek, prof. PŚ
Sułek Wojciech, profesor uczelni
tel. 32 237 1157 wew. 42
e-mail: wojciech.sulek@polsl.pl
ORCID: 0000-0003-3462-0657
Wydział Automatyki, Elektroniki i Informatyki
44-100 Gliwice, Akademicka 16, pokój 916
Publikacje
- J. Hyla, W. Sułek, Dekoder LDPC implementowany w mikrokontrolerze dla systemów Internetu Rzeczy, Przegląd Elektrotechniczny, Sigma NOT, vol. 99, nr 4, 2023, s. 133-139, DOI:10.15199/48.2023.04.23.
- J. Hyla, W. Sułek, Energy-efficient Raptor-like LDPC coding scheme design and implementation for IoT communication systems, Energies, vol. 16, nr 12, 2023, Numer artykułu: 4697, s. 1-21, DOI:10.3390/en16124697.
W. Sułek, The design of structured LDPC codes with algorithmic graph construction, Bulletin of the Polish Academy of Sciences: Technical Sciences 2022 (Early Access), DOI: 10.24425/bpasts.2022.141592.
J. Hyla, W. Sułek, W. Izydorczyk, L. Dziczkowski, W. Filipowski, Efficient LDPC Encoder Design for IoT-Type Devices, Applied Sciences 2022, 12(5), art. no. 2558; DOI: 10.1063/5.0048362.
- M. Kuc, W. Sułek, D. Kania, Low power QC-LDPC decoder based on Token Ring architecture, Energies, vol. 13, 2020, pp. 1–18 (art. no. 6310).
- M. Kuc, W. Sułek, D. Kania, FPGA-Oriented LDPC Decoder for Cyber-Physical Systems, Mathematics, vol. 8, 2020, pp. 1–15 (art. no. 723).
- W. Sułek, Protograph Based Low-Density Parity-Check Codes Design with Mixed Integer Linear Programming, IEEE Access, vol. 7, 2019, pp. 1424–1438.
- W. Sułek, M. Kucharczyk, QC-LDPC Codes with fast encoding for error control in NAND flash memories, 2018 International Conference on Signals and Electronic Systems (ICSES), Kraków, Poland, September 10-12, 2018, pp. 37–42.
- W. Sułek, Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes, IEEE Communications Letters, vol. 20, No. 9, 2016, pp. 1705–1708.
- W. Sułek, M. Kucharczyk, Partial Parallel Encoding and Algorithmic Construction of Non-Binary Structured IRA Codes, China Communications, vol. 13, No. 8, 2016, pp. 103–116.
- W. Sułek, Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation, Circuits, Systems, and Signal Processing, vol. 35, No. 11, 2016, pp. 4060–4080.
- W. Sułek, M. Kucharczyk, Column Weights Optimization for Semi-Regular Nonbinary LDPC Codes, 38th International Conference on Telecommunications and Signal Processing (TSP) 2015, Prague, Czech Republic, July 9-11, 2015, pp. 172–176.
- W. Sułek, M. Kucharczyk, G. Dziwoki, GF(q) LDPC decoder design for FPGA implementation, 10th IEEE Consumer Communications and Networking Conference (CCNC) 2013, Las Vegas, NV, USA, January 11–14, 2013, pp. 460–465.
- W. Sułek, On the Overflow Problem in Finite Precision Turbo Decoding Message Passing, IEEE Transactions on Communications, vol. 60, No. 5, 2012, pp. 1253–1259.
- W. Sułek, Pipeline processing in low-density parity-check codes hardware decoder, Bulletin of the Polish Academy of Sciences Technical Sciences, vol. 59, No. 2, 2011, pp. 149–155.
