Pracownicy

Short BIO

• Master's degree in electronics specialization electronic equipment completed in June 1988 (thesis: "Automation of digital circuit design based on non-monotonic logics").
• PhD thesis ”Automated generation of models of electronic digital integrated circuits in VHDL in the absence of complete design information concerning the object being modeled” (supervisor Jan Chojcan, PhD, DSc) defended with honors 3rd June 1997.
• Habilitation monography ”Heuristic techniques in electronic systems modeling and verification. Selected problems” published in 2012, DSc degree awarded by the Council of the Faculty of Automatic Control, Electronics and Computer Sciences of the Silesian University of Technology in 9th April 2013.
• University Professor in Silesian University of Technology since 1st December 2018.

Positions

• Head of the Department of Electronics, Electrical Engineering and Microelectronics (RAu11) since 2021 r.
• Member of the Recruitment Committee for the Doctoral School of Silesian University of Technology.
• Coordinator of the PhD studies for electronics and telecommunication in the Faculty of Automatic Control, Electronics and Computer Sciences.
• Manager of the project CyPhiS – the project of contemporary, interdyscyplinary PhD studies in the field of cyber-physical systems implemented in the Faculty of Automatic Control, Electronics and Computer Sciences. (2018-2022)

Scientific interest

• Modeling, design and simulation of electronic embedded systems and mixed analog-digital systems in system and hardware description languages.
• Time-predictable real-time systems – design, modeling and dissipated power optimization.
• Application of programmable hardware platforms to accelerate computations and analyses of data coming from computational biology and genetics..
• Formal verification methodologies.
• SAT Solving.
• Expert systems, applications of AI techniques in electronic systems design, reasoning in the absence of complete information.
• Cyber-physical systems.

Selected achievements

• Author of about 90 scientific publications.
• Reviewer of several journals noted in JCR base.
• Organizer of 4 international scientific conferences (IFAC PDES and IEEE ICSES) (listed in the database Web of Science).
• IEEE Member since 2006 (from 2011 senior member).
• Member of Polish Association of Theoretical and Applied Electrical Engineering (Polskiego Towarzystwa Elektrotechniki Teoretycznej i Stosowanej - PTETiS) and the Commission of Electronics of Polish Academy of Science (PAN) regional branch in Katowice since 1997.
• Member of CHESS group (Center for Hybrid and Embedded Software Systems) from University of California in Berkeley in 2007-2010 (PRET project).
• Supervisor of 1 completed (defended) and 1 currently being in progress doctoral dissertation.

Teaching accomplishments

• Supervisor of above 20 MSc and BSc thesis.
• Preparation of new lectures, development of new laboratory positions and new tutorials in Polish and English, among others:
  - Methods of concurrent hardware and software design,
  - Fundamentals of signal processing,
  - Signals and systems,
  - System level modeling and design,
  - Design of analog-digital integrated circuits,
  - Fundamentals of signal processing.
• Development of a doctoral program in cyber-physical systems, including in detail two lectures
• Development of a doctoral program in cyber-physical systems, including in detail two lectures:
  - Modeling and simulation physical-discrete systems on the example of complex mixed analog/digital systems,
  - Contemporary verification methodologies of cyber-physical embedded systems.

International cooperation

• Czech Republic, Summer School on Design Automation of Electronic Systems, Prague 8-13.07.1996.
• 3-month internship in USA, Visiting Scholar position at Department of Electrical Engineering and Computer Science in University of California, Berkeley 26.08-30.11.2007 r invited by Prof. L.A. Zadeh and Dean of EECS UC Berkeley Prof. E.A. Lee.
• In the period 2006–2012 reviewer of research projects on behalf of the European Commission.
• Participation in the DCPS project with the University of Cottbus, Germany (2013-2015).

Collaboration with industry

• Collaboration with companies CADENCE, Aldec Poland, ARM Poland and Evatronix POLAND.

Awards and distinctions

• 7 times featured by the rector of Silesian University of Technology for: research (2), teaching (4) and organizational activity (1).
• Wyróżniony brązowych krzyżem zasługi w 2002.
• Wyróżniony Odznaką Zasłużony dla Politechniki Śląskiej w 2008.
• Wyróżniony Medalem Komisji Edukacji Narodowej w 2017.

Selected research papers

1. Grabowiecki, A. Pułka: Non-monotonic Reasoning in Digital Circuit Design, In: G.Odawara (Ed.): CAD Systems Using AI Techniques, North-Holland, 1989.
2. Pułka, A. Pawlak: A Technique For Generation of VITAL Models Handling Incomplete Information, Proceedings of the 22nd EUROMICRO Conference Beyond 2000: Hardware/Software Design Strategies Short Contributions, IEEE Computer Society Press, Los Alamitos, California 1997, pp. 132-137.
3. Pułka, A. Pawlak: Experiences with VITAL Code Generator Controlled by a Nonmonotonic Inference Engine, Proceedings of 2nd WORKSHOP on Libraries Component Modelling and Quality Assurance with CHDL'97 and VHDL Forum,Toledo, Spain, April 20-25, 1997.
4. Dąbrowski, A. Pułka: Discrete Approach to PWL Analog Modeling in VHDL Environment, Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, Vol. 16, No. 2, 1998 pp.91-99.
5. Pułka: Modeling Assistant - a Flexible VCM Generator in VHDL, In R.Seepold, N.Martinez (Ed.): Virtual Components Design and Reuse, Kluwer Academic Publishers, Boston Hardbound 2000, pp.171–182.
6. Dąbrowski, A. Pułka - Efficient Modeling of Analog and Mixed A/D Systems via Piece-wise Linear Technique, Electronic Chips & System Design, edited by Jean Mermet, Kluwer Academic Publisher, The ChDL Series, Boston 2001, pp.43-54.
7. Pułka, SystemC Models Generation Based on Libraries of Templates, IEEE International Symposium on Circuits and Systems ISCAS 2006, Kos Island, Greece 2006, pp. 2693-2696.
8. Pułka, A. Milik: VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams, Proceedings of the FDL’08 Conference, Stuttgart, GERMANY, Sept. 23-25 2008, pp.118–123.
9. Pułka, P. Kłosowski: Polish Speech Processing Expert System Incorporated into the EDA Tool, in: Human-Computer Systems Interaction Backgrounds and Applications, Series: Advances in Intelligent and Soft Computing , Vol. 60, Hippe, Z. S.; Kulikowski, J. L. (Eds.), Springer Verlag 2009, ISBN: 978-3-642-03201-1, pp. 281–293.
10. Pułka: Decision Supporting System Based on Fuzzy Default Reasoning, Proceedings of the IEEE HSI’09 Human Systems Interaction Conference, Catania, Italy, May 21-23, 2009, pp. 32–39.
11. Pułka and A. Milik: Hardware model of the commonsense reasoning based on Fuzzy Default Logic, Proceedings of IEEE HSI’10 Human Systems Interaction Conference, Rzeszów, Poland, May 13 - 15, 2010, pp.34–41. (Best Paper Award in the field of Artificial Intelligence) wydane w Z.S.Hippe et al. (Eds): Human-Computer Systems Interaction, Part II, Springer-Verlag Berlin Heidelberg 2012, pp.325-343.
12. Pułka:. Two Heuristic Algorithms for Test Point Selection in Analog Circuits Diagnoses, Metrology and Measurement Systems, 18(1), pp. 115–128, 2011.
13. Pułka, Ł. Golly, A. Milik: SystemC Hardware-Software Design and Simulation Platform Based on AMBA Bus, Proceedings of MIXDES 2011 – The 18th International Conference on Mixed Design of Integrated Circuits and Systems, Gliwice, POLAND June 16-18 2011, pp. 664–649. (The most valuable paper)
14. Milik, A. Pułka: Automatic Implementation of Arithmetic Operation in Reconfigurable Logic Controllers, Proceedings of ECCTD 2011 Conference, Linköping, SWEDEN, Aug.27-30, pp. 721–724.
15. Pułka, A.Milik:. Measurement Aspects of the Genome Patterns Investigations – Hardware Implementation, Metrology and Measurement Systems, 19(1), 2012, pp. 49–62.
16. Pułka and A. Milik: Hardware Implementation of Fuzzy Default Logic, in: Human-Computer Systems Interaction Backgrounds and Applications II, Series: Advances in Intelligent and Soft Computing , Vol. 99, Hippe, Z. S.; Kulikowski, J. L. (Eds.), Springer Verlag 2012, ISBN: 978-3-642-23171-1, pp. 325–343.
17. Pułka: Searching Strategies Selection for Solving 3-SAT Problems, International Journal of Applied Mathematics and Computer Science, 24(2), 2014, pp. 283–297.
18. Ł. Golly, A. Milik, Pułka: High Level Model of Time Predictable Multitask Control Unit, IFAC-PapersOnLine, Volume 48, Issue 4, 2015, pp. 348–353, ISSN 2405-8963, http://dx.doi.org/10.1016/j.ifacol.2015.07.059.
19. Pułka, Ł. Golly: Some Issues Concerning Design Space Exploration in Time Predictable Embedded Systems, Proceedings of 2016 International Conference on Signals and Electronic Systems (ICSES), Krakow, 2016, pp. 231-236.
20. Pułka A.: "JumpSAT Based System Verification Scenarios," 2018 International Conference on Signals and Electronic Systems (ICSES), Kraków, 2018, pp. 301–306. doi: 10.1109/ICSES.2018.8507290
21. Malcher, A. Kristof and A. Pułka, "40 nm CMOS Implementation of Basic Building Blocks for Programmable Current Mode Devices," 2018 International Conference on Signals and Electronic Systems (ICSES), Kraków, 2018, pp. 27–32. doi: 10.1109/ICSES.2018.8507286
22. Antolak and A. Pułka, "Flexible hardware approach to multi-core time-predictable systems design based on the interleaved pipeline processing," in IET Circuits, Devices & Systems, vol. 14, no. 5, pp. 648-659, 8 2020, doi: 10.1049/iet-cds.2019.0521.
23. Antolak, A. Pułka - The Hierarchical model of a flexible predictable system for time critical data processing, Computer Networks 2020, Studia Informatica (zaakceptowane)
24. Kristof, A.Malcher, A. Pułka, " Digitally Programmable Modified Current Differencing Transconductance Amplifier in 40 nm Technology – Design Flow, Parameters Analyses and Applications," in IET Circuits, Devices & Systems, vol. 14 , no. 8, pp. 1272–1282, 2020, doi: 10.1049/iet-cds.2019.0494.
25. Antolak and A. Pułka, "Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems," in IEEE Access, vol. 9, pp. 121111-121127, 2021, doi: 10.1109/ACCESS.2021.3108912.